業(yè)界領(lǐng)先的性能功耗比
Virtex? UltraScale+? 器件不僅提供 3X 的系統(tǒng)性能功耗比，而且還提供了支持廣泛應(yīng)用的系統(tǒng)集成度和帶寬，可充分滿足 1+ Tb/s 有線通信、高性能計(jì)算以及雷達(dá)應(yīng)用波形處理等需求。 Virtex UltraScale+ 系列可在性能、帶寬以及更低時(shí)延方面實(shí)現(xiàn)一步功能提升，可充分滿足要求大規(guī)模數(shù)據(jù)流以及數(shù)據(jù)包處理的系統(tǒng)需求。Virtex UltraScale+ 器件建立在UltraScale? 架構(gòu)的 ASIC-class 優(yōu)勢基礎(chǔ)之上，專門針對 Vivado? Design Suite進(jìn)行了協(xié)同優(yōu)化，可充分發(fā)揮 UltraFAST?設(shè)計(jì)方法優(yōu)勢，加速產(chǎn)品上市進(jìn)程。

系列包括:

TSMC 的 16FinFET+ 工藝技術(shù)可顯著提高性能功耗比
UltraRAM 可將片上存儲(chǔ)器密度提高 8 倍，從而可提供最低的功耗、最大的靈活性以及最高的可預(yù)測性能
PCI Express? Gen 3x16 和 Gen 4x8 集成塊支持高帶寬接口要求
virtex-ultrascale+
值 特性
可編程的系統(tǒng)集成 
超過 400 Mb 的 UltraRAM 片上存儲(chǔ)器集成
集成型 100G 以太網(wǎng) MAC 以及 RS-FEC 和 150GInterlaken 內(nèi)核
適用于 PCI Express Gen 3x16 與 Gen 4x8 的集成塊
提升的系統(tǒng)性能 
高利用率使速度提升四個(gè)等級
高達(dá) 128-33G 的收發(fā)器可實(shí)現(xiàn) 7 Tb 的串行帶寬
中間檔速率等級芯片可支持 2,666 Mb/s DDR4
BOM 成本削減 
1 Tb MuxSAR 轉(zhuǎn)發(fā)器卡減少比例為 5:1
適用于片上存儲(chǔ)器集成的 UltraRAM
VCXO 與 fPLL (分頻鎖相環(huán)) 的集成可降低時(shí)鐘組件成本
總功耗削減 
與 7 系列 FPGA 相比，功耗銳降 60%
電壓縮放選項(xiàng)支持高性能與低功耗
緊密型邏輯單元封裝減小動(dòng)態(tài)功耗
加速設(shè)計(jì)生產(chǎn)力 
從 20nm 平面到 16nm FinFET 的無縫引腳遷移+
與 Vivado 設(shè)計(jì)套件協(xié)同優(yōu)化，加快設(shè)計(jì)收斂
適用于智能 IP 集成的 SmartConnect 技術(shù)

Notes:
1. Relative to the effective logic utilization demonstrated in the competition’s 20nm product portfolio.
2. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.
3. The B784 package is only offered in 0.8mm ball pitch. All other packages are 1.0mm ball pitch.
 
Disclaimer: This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or services not yet available for sale, and provided solely for information purposes and are not intended,
or to be construed, as an offer for sale or an attempted commercialization of the products and/or services referred to herein. Please contact your Xilinx representative for the latest information.
 
 
 General-Purpose Devices Signal Processing Optimized Devices
 Device Name KU3P KU7P KU11P KU15P KU5P KU9P KU13P
Logic
Effective LEs(1)
 (K) 245 485 630 1,100 455 570 715
Logic Cells (K) 205 403 523 915 380 477 597
CLB Flip-Flops (K) 234 461 597 1,045 434 548 683
CLB LUTs (K) 117 230 299 523 217 274 341
Memory
Max. Distributed RAM (Mb) 3.6 6.2 8.9 9.6 6.3 8.8 11.0
Total Block RAM (Mb) 5.1 11.0 21.1 34.6 16.9 32.1 26.2
 UltraRAM (Mb) 18.0 27.0 22.5 36.0 18.0 0 31.5
Integrated
IP
 
DSP Slices 1,056 1,728 2,928 1,968 1,824 2,520 3,528
Video Codec Unit 1 1 0 0 0 0 0
PCIe? Gen3 x16 / Gen4 x8 2 2 4 5 1 0 0
150G Interlaken 0 0 2 4 0 0 0
100G Ethernet w/RS-FEC 0 0 1 4 0 0 0
I/O
Max. Single-Ended HD I/Os 96 96 96 96 72 96 96
Max. Single-Ended HP I/Os 208 416 416 572 208 208 208
GTH 16.3Gb/s Transceivers 16 24 32 44 0 28 28
GTY 32.75Gb/s Transceivers 0 0 20 32 16 0 0
 
Footprint(2)
 
Dimensions
(mm)
HD I/O, HP I/O, GTH 16.3Gb/s, GTY 32.75Gb/s
 
 
 
 
 Packaging
 
 
 
 
 
 B784(3)
23x23 96, 208, 16, 0
C676 27x27 96, 208, 16, 0 96, 208, 16, 0
D676 27x27 72, 208, 0, 16
D900 31x31 96, 312, 16, 0 96, 312, 16, 0
E900 31x31 96, 208, 28, 0 96, 208, 28, 0
D1156 35x35 96, 416, 16, 0 96, 520, 16, 0
E1156 35x35 96, 416, 24, 0 96, 416, 24, 0
E1517 40x40 96, 416, 32, 20 96, 416, 32, 24
E1760 42.5x42.5 96, 572, 32, 24
F1760 42.5x42.5 96, 416, 44, 32 ? Copyright 2015 Xilinx
.
Disclaimer: This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or services not yet available for sale, and provided solely for information purposes and are not intended,
or to be construed, as an offer for sale or an attempted commercialization of the products and/or services referred to herein. Please contact your Xilinx representative for the latest information.
 
 Page 2
Virtex? UltraScale+? FPGAs
 Device Name VU3P VU5P VU7P VU9P VU11P VU13P
Logic
Effective LEs(1)
 (K) 830 1,260 1,655 2,485 2,575 3,435
Logic Cells (K) 690 1,051 1,379 2,069 2,147 2,863
CLB Flip-Flops (K) 788 1,201 1,576 2,364 2,454 3,272
CLB LUTs (K) 394 601 788 1,182 1,227 1,636
Memory
Max. Distributed RAM (Mb) 12.1 18.4 24.1 36.1 34.8 46.4
Total Block RAM (Mb) 25.3 36.0 50.6 75.9 70.9 94.5
 UltraRAM (Mb) 90.0 132.2 180.0 270.0 324.0 432.0
Integrated
IP
DSP Slices 2,280 3,474 4,560 6,840 8,928 11,904
PCIe? Gen3 x16 / Gen4 x8 2 4 4 6 3 4
150G Interlaken 3 4 6 9 9 12
100G Ethernet w/ RS-FEC 3 4 6 9 6 8
I/O
Max. Single-Ended HP I/Os 520 832 832 832 624 832
GTY 32.75Gb/s Transceivers 40 80 80 120 96 128
 
 Footprint(2,3)
 Dimensions
(mm)
HP I/O, GTY 32.75Gb/s
Footprint
Compatible
with 20 nm
UltraScale
Devices
C1517 40x40 520, 40
A2104
47.5x47.5 832, 52 832, 52 832, 52
 52.5x52.5(4)
 832, 52
B2104
47.5x47.5 702, 76 702, 76 702, 76 624, 76
 52.5x52.5(4)
 702, 76
C2104
47.5x47.5 416, 80 416, 80 416, 104 416, 96
 52.5x52.5(4)
 416, 104
A2577 52.5x52.5 448, 120 448, 96 448, 128
Notes:
1. Relative to the effective logic utilization demonstrated in the competition’s 20nm product portfolio.
2. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.
3. All packages are 1.0mm ball pitch.
4. These 52.5x52.5mm packages have the same PCB ball footprint as the 47.5x47.5mm packages and are footprint compatible.
 
 ? Copyright 2015 Xilinx
.
Page 3
UltraScale+ Device Ordering Information
 
 
E = Extended (Tj = 0°C to +100°C)
I = Industrial (Tj = –40°C to +100°C)
Important: Verify all data in this document with the device data sheets found at For valid part/package combinations,
go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os Tables